Publishing: May 2021 | Report Code: SE10406 | Available Format: PDF
The global wafer level packaging (WLP) market is growing with a significant rate, due to changes in electronics industry infrastructure and increasing demand for portable consumer devices. However, the solder joint thermal cycling reliability of standard wafer level packaging is restraining the growth of the global wafer level packaging market. The Asia-Pacific wafer level packaging market is growing with a significant rate, due to the increasing demand for tablets and smartphones in the region.
In the semiconductor packaging industry, the wafer level packaging market is growing with the fastest rate, due to the increasing demand for smaller, lighter, faster, and less expensive electronic products, with low cost packaging and high performance. The rapid advancements in integrated circuit fabrication are also supporting the growth of the wafer level packaging technology in the semiconductor packaging industry. As the wafer level packaging is intrinsically chip size package, its form factor is very small. In comparison to die level packaging such as wird-bond type packaging, the wafer level packaging has low packaging cost. With the increased in wafer size, or decreased die size in die level packaging, the packaging cost becomes higher than manufacturing cost of IC. Whereas, in wafer level packaging, its packaging cost per wafer is comparable to the total IC cost. This means that wafer level packaging is more cost-effective with increased wafer size or decreased die size. Due to such advantages, most of the integrated circuit manufacturers are incorporating wafer level packaging in their designs.
As wafer level packaging is intrinsically a chip sized pack, which has highest potential for future single chip packages. Wafer level testing and wafer fabrication replaces all the testing and packaging operations of the dice. Hence, wafer level packaging becomes more cost effective, due to the increasing wafer size or decreasing die size. However, solder ball consistency subjected to temperature cycling, becomes the weakest point of the wafer level packaging, due to intrinsic mismatch of the coefficient of thermal expansion between plastic PCB material and silicon chip.
On the basis of integration, the global wafer level packaging market can be categorized as fan-out WLP, fan-in WLP, integrated passive device, and through-silicon via. On the basis of technology, the global wafer level packaging market can be categorized as 3D wafer-level packaging, compliant WLP, conventional chip scale package, flip chip, nano wafer level packaging and wafer level chip scale package. The global wafer level packaging market is also categorized on the basis of applications, as defense and aerospace, consumer electronics, medical, automotive and industrial.
Some of the advantages of wafer level packaging over traditional packaging methods are smaller size, superior performance, and design flexibility. Structural support, clearance for high frequency operation, and mechanical protection are provided by the sealed air cavity that surrounds die. Wafer level packaging offers reduced power consumption, minimal parasitic and extended battery life. Wafer level packaging is thinner than traditional packaging methods, with filters of around 0.13 millimeter. It is one of the major factors considered while designing thinner mobile devices.
Some of the competitors in the global wafer level packaging market are ChipMOS TECHNOLOGIES INC., IQE PLC, Amkor Technology Inc., Siliconware Precision Industries Co. Ltd., TriQuint Semiconductor Inc., China Wafer Level CSP Co. Ltd., Jiangsu Changjiang Electronics Technology Co. Ltd., Powertech Technology Inc., Fujitsu Limited, Chipbond Technology Corporation, Nemotek Technologie S.A., and STATS ChipPAC Ltd.
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